1. Field of the Invention
The present invention relates to an imaging device, and more particularly, to a solid-state imaging device including an analog-to-digital (AD) converting circuit for each column.
Priority is claimed on Japanese Patent Application No. 2011-145110, filed on Jun. 30, 2011, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, solid-state imaging devices have been used in various devices such as still cameras, video cameras, medical endoscopic cameras, industrial endoscopic cameras, high-performance visual sensors for robots, and perimeter monitoring visual sensors for vehicles. Charged coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors have been known as the solid-state imaging devices used in these devices.
A CMOS image sensor can be manufactured by the same technique as a general semiconductor manufacturing process, and thus the CMOS image sensor can have various functions by embedding various functional circuits in a sensor. For example, as an image sensor in which a functional circuit is embedded in a sensor, Japanese Unexamined Patent Application, First Publication No. H9-238286 discloses a technique related to an image sensor in which an AD converting circuit is provided for each column of a pixel array arranged in the form of a matrix, and a digital signal which has been subjected to AD conversion is output in units of rows.
In the image sensor in which an AD converting circuit is provided for each column, for example, a signal transfer circuit aiming for transfer of a signal is disposed between the AD converting circuit and a signal line through which a digital signal (signal information) is output to the outside. For example, the signal transfer circuit of this aim includes a latch circuit that temporarily latches or holds the digital signal output from the AD converting circuit and a switch for sequentially outputting the digital signal (signal information) to the outside of the image sensor.
FIG. 15 is a circuit connection diagram illustrating an example of a connection of components related to transfer of a digital signal in an image sensor of a related art. The signal transfer circuit illustrated in FIG. 15 temporarily holds digital signals output from a digital signal generating circuit, which outputs a digital signal (signal information), such as an AD converting circuit arranged for each column, and then sequentially outputs the digital signals (signal information) to the outside.
An AD converting circuit 111 is arranged in each of first to mth columns of a pixel array (not shown) and converts pixel analog signals output from pixels into an n-bit digital signal, and outputs respective bit signals to a latch circuit 211 through different lines. In the following description, a number in “( ): parentheses” following a symbol represents a bit of a digital signal. For example, a second bit of a digital signal is represented by “(2).”
Each latch circuit 211 holds respective bits of the n-bit digital signal output from the AD converting circuit 111 in internal latch units bits (1) to (n).
Signal transfer lines 311 are connected with the latch circuits 211 of respective columns via the switches SW(1) to SW(m). The respective bits of the signal transfer lines 311 correspond to the latch units bit(1) to bit(n) in the latch circuit 211 of each column, and the latch unit of the same bit in the latch circuit 211 of each column is connected to the signal transfer line 311 of the same bit.
In response to a control of the switches SW(1) to SW(m) from a driving control circuit (not shown), the digital signals held in the latch circuit 211 of each column are sequentially output to the outside of the sensor, a signal processing circuit in the sensor, or the like.
Here, transfer control of the digital signal (signal information) in the signal transfer circuit is described. FIG. 16 is a timing chart illustrating a driving timing when the digital signal is output from the signal transfer circuit in the image sensor of the related art. The timing chart illustrated in FIG. 16 illustrates a driving timing when the digital signals (signal information) held in the latch circuit 211 of the signal transfer circuit illustrated in FIG. 15 are sequentially output to the outside.
When the digital signals (signal information) held in the latch circuit 211 are output, in a data transfer time period, the switch SW(1) is first turned on, and thus the latch units bit(1) to bit(n) of the latch circuit 211 of a first column are connected to the signal transfer lines 311. Through this operation, the digital signals (signal information) held in the latch circuit 211 of the first column are output to the signal transfer lines 311. Thereafter, a switching operation to sequentially turn on the switches SW(2) to SW(m) is performed, and the digital signals (signal information) held in the corresponding latch circuits 211 are sequentially output to the signal transfer line 311.